1. Field of the Invention
The present invention relates to a nonvolatile ferroelectric memory device, and more particularly, to a sensing amplifier of a nonvolatile ferroelectric memory device.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 shows hysteresis loop of a general ferroelectric. As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described. FIG. 2 shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected with a drain of the transistor T1 and second terminal is connected with the plate line P/L.
The data input/output operation of the related art nonvolatile ferroelectric memory device will now be described. FIG. 3a is a timing chart illustrating the operation of the write mode of the related art nonvolatile ferroelectric memory device, and FIG. 3b is a timing chart illustrating the operation of read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor. A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor.
The reading operation of data stored in a cell by the above operation of the write mode will now be described. If an externally applied chip enable signal CSBpad is activated from high state to low state; all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the ferroelectric memory. If the logic value xe2x80x9c0xe2x80x9d is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. In other words, if the data is destroyed, the xe2x80x9cdxe2x80x9d state is transited to an xe2x80x9cfxe2x80x9d state as shown in hysteresis loop of FIG. 1. If the data is not destroyed, xe2x80x9caxe2x80x9d state is transited to the xe2x80x9cfxe2x80x9d state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value xe2x80x9c1xe2x80x9d is output in case that the data is destroyed while the logic value xe2x80x9c0xe2x80x9d is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
FIG. 4 is a block diagram showing the related art nonvolatile ferroelectric memory device. As shown in FIG. 4, the related art nonvolatile ferroelectric memory device includes a main cell array 41, a reference cell array 42 assigned on a lower part of the main cell array 41, a wordline driver 43 formed at a side of the main cell array for applying a driving signal to the main cell array 41 and the reference cell array 42, and a sensing amplifier 44 formed at a lower part of the reference cell array 42.
The wordline driver 43 applies the driving signal to a main wordline of the main cell array 41 and a reference wordline of the reference cell array 42. The sensing amplifier 44 includes a plurality of sensing amplifiers and amplifies signals of a corresponding bitline B/L and bit bar line BB/L.
The operation of the related art nonvolatile ferroelectric memory device will now be described with reference to FIG. 5. FIG. 5 is a partially detailed view of FIG. 4. As shown in the drawing, the main cell array has a folded bitline structure in the same manner as DRAM.
Also, the reference cell array 42 has a folded bitline structure and includes a reference cell wordline and a reference cell plate line in pairs. At this time, reference cell wordline and the reference cell plate line pairs are defined as RWL_1 and RPL_1, and RWL_2 and RPL_2, respectively.
When the main cell wordline MWL_Nxe2x88x921 and the main cell plate line MPL_Nxe2x88x921 are activated, the reference cell wordline RWL_1 and the reference cell plate line RPL_1 are activated. Therefore, data in the main cell is loaded into the bitline B/L and data in the reference cell is loaded into the bit bar line BB/L.
When the main cell wordline MWL_N and the main cell plate line MPL_N are activated, the reference cell wordline RWL_2 and the reference cell plate line RPL_2 are activated. Therefore, data in the main cell is loaded into the bit bar line BB/L and data in the reference cell is loaded into the bitline B/L.
The reference voltage REF by the reference cell exists between the bitline levels B_H (high) and B_L(low) by the main cell. To generate the reference voltage REF between the bitline levels B_H and B_L, the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d may be stored in a capacitor of the reference cell. When the logic value xe2x80x9c1xe2x80x9d is stored in the capacitor of the reference cell, the size of the capacitor of the reference cell is smaller than that of the capacitor of the main cell. When the logic value xe2x80x9c0xe2x80x9d is stored in the capacitor of the reference cell, the size of the capacitor of the reference cell is greater than that of the capacitor of the main cell.

FIG. 6 is a diagram illustrating one of the plurality of sensing amplifiers constituting the sensing amplifier of FIG. 4. As shown in FIG. 6, the related art sensing amplifier has a structure of a latch type sensing amplifier.
In other words, the sensing amplifier in FIG. 6 includes two PMOS transistors and two NMOS transistors, and these PMOS and NMOS transistors have latch type inverter structures. The first PMOS transistor MP1 and the second PMOS transistor MP2 face each other. An output terminal of the first PMOS transistor MP1 is connected to a gate of the second PMOS transistor MP2, and an output terminal of the second PMOS transistor MP2 is connected to a gate of the first PMOS transistor MP1. An SAP signal is commonly applied to input terminals of the first and second PMOS transistors MP1 and MP2. The SAP signal is an active signal that activates the first and second PMOS transistors MP1 and MP2.
The first NMOS transistor MN1 is connected to the output terminal of the first PMOS transistor MP1 in series. The second NMOS transistor MN2 is connected to the output terminal of the second NMOS transistor MN2 in series. The output terminal of the second NMOS transistor MN2 is connected to a gate of the first NMOS transistor MN1, and the output terminal of the first NMOS transistor MN1 is connected to a gate of the second NMOS transistor MN2.
An SAN signal is commonly applied to input terminals of the first and second NMOS transistors MN1 and MN2. The SAN signal is an active signal that activates the first and second NMOS transistors MN1 and MN2.
The output terminals of the first PMOS transistor MP1 and first NMOS transistor MN1 are commonly connected to the bitline B_N. The output terminals of the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected to the next bitline B_N+1.
The output of the sensing amplifier is respectively connected to the bitlines B_N and B_N+1 to be input and output to the main cell and the reference cell, respectively, thereby enabling input/output to the main cell and the reference cell.
The SAP signal, the SAN signal, and the signals of B_N and B_N+1 are all maintained at xc2xd Vcc for a precharge period when the sensing amplifier is not active. On the other hand, the SAP signal is pulled-up at high level and the SAN signal is pulled-down at low level.
As described above, the related art nonvolatile ferroelectric memory device has various disadvantages. Since the reading and writing operation of data is performed using different data buses, a plurality of data buses are required. Accordingly, efficient layout of the FRAM is difficult. In addition, stability is decreased in amplification during reading and writing operation.
An object of the present invention is to provide a sensing amplifier of a nonvolatile ferroelectric memory device that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide a sensing amplifier that amplifies cell data using three stages in a nonvolatile ferroelectric memory device.
Another object of the present invention is to provide a sensing amplifier in a nonvolatile ferroelectric memory device that uses a single data bus for reading and writing operations.
Another object of the present invention is to provide a sensing amplifier in a nonvolatile ferroelectric memory device that has a reduced size.
Another object of the present invention is to provide a sensing amplifier in a nonvolatile ferroelectric memory device that has an increased stability in amplification during reading and writing operations.
Another object of the present invention is to provide a sensing amplifier of a nonvolatile ferroelectric memory device in which a data bus is commonly used when reading and writing data to obviate separate data buses and increase stability in amplification.
To achieve at least the above objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a sensing amplifier of a nonvolatile ferroelectric memory device having three-stage amplification portions for amplifying signals of bitlines, according to the present invention includes a first amplification stage that amplifies the signals of the bitlines, a first data bus commonly used for reading and writing of data that transfers an output signal of the first amplification stage, a second amplification stage that amplifies a signal of the first data bus, a second data bus commonly used for reading and writing of data that transfers an output signal of the second amplification stage and a third amplification stage that amplifies a signal of the second data bus.
To achieve at least the above objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a sensing amplifier of a nonvolatile ferroelectric memory device that includes a first amplification stage that amplifies signals of a plurality of bitlines, a first data bus that transfers a first signal to and from the first amplification stage for writing and reading of data, respectively, a second amplification stage that amplifies the first signal of the first data bus, a second data bus that transfers a second signal to and from the second amplification stage for writing and reading of data, respectively, and a third amplification stage that amplifies the second signal of the second data bus.
To achieve at least the above objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a memory device that includes a plurality of cell arrays in a matrix arrangement, first amplification stages respectively positioned at lower and upper portions of a corresponding one of the cell arrays, first data buses commonly coupled to the first amplification stages disposed on the same row of the plurality of cell arrays, wherein the first data buses transfers signals of the first amplification stages, a second amplification stage that amplifies the signals transmitted through the first amplification stage, first switches coupled with one of the first and second amplification stages to switch output signals thereof, a third data bus that transfers the output signals of the second amplification stage, and a third amplification stage that amplifies signals of the third data bus.
To achieve at least the above objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a nonvolatile ferroelectric memory device that includes a first split wordline driver, first and second cell arrays, wherein the first split wordline driver is between the cell arrays to drive wordlines thereof, first amplification stages each respectively positioned on at least one side of a corresponding one of the cell arrays, wherein the first amplification stages are coupled to bitlines of the respective cell arrays, a first data bus coupled to each of the first amplification stages, a second amplification stage coupled to the first data bus, a second data bus coupled to the second amplification stage, and a third amplification stage coupled to the second data bus.
To achieve at least the above objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described,
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.